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Hardware interview practice

Drive random back-pressure

EasyVerification UtilitiesSystemVerilog

Drive ready high on approximately pct_ready percent of cycles to create randomized back-pressure.

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Reviewed example

Work through one case

Input
pct_ready=25; random draws over four clock edges=[12,80,24,60] from 0..99
Expected output
ready=[1,0,1,0]

A fresh clocked draw is high only below the clamped 25-percent threshold; pct_ready 0 and 100 become deterministic low and high limits.

What to cover

Requirements

  1. Update ready on the interface clock.
  2. Accept a percentage from 0 through 100.
  3. Generate a fresh decision each cycle.
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