Hardware interview practice
How to Drive a Ready/Valid Interface Correctly
Implement the core of a UVM driver for a single-beat ready/valid interface. Present one sequence item, hold its payload stable while stalled, and finish the item only after a real handshake.
Example
driver owns payload A; sampled ready values on successive clocks are X,0,1report unknown ready; hold valid/data A; then complete exactly one handshake on the third edgeExplanation: Only known-high ready accepts the beat; X and zero both preserve the same asserted payload and defer item_done().
Reasoning requirements
- A beat completes only on a sampled clock edge where valid and ready are both exactly 1.
- Once valid is asserted, data and control must not change until that handshake.
- Treat X or Z on ready as not-ready and report it instead of accepting the beat.
- Leave the interface idle between items unless a separate pipelining policy says otherwise.
Concise answer
The answer and the key reason
Deeper explanation
Work through the implementation and tradeoffs
A ready/valid transfer exists only on a clock edge that samples both controls high. Therefore a stalled beat is still the same in-flight beat: valid stays asserted and payload and control stay unchanged. Repeatedly rewriting the payload inside the wait loop risks presenting multiple logical values before any one of them has been accepted.
A clocking block gives the testbench defined drive and sample regions, avoiding races with the DUT. Treat an unknown or high-impedance ready as refusal and report it, because optimistic acceptance would hide interface corruption. Once the accepting edge occurs, return the bus to idle and then notify the sequencer that the item is complete.
What to remember
- Handshake only on valid and ready
- Hold payload stable during stalls
- Acknowledge after acceptance
Practice the complete prompt
