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Hardware interview practice

Monitor a ready/valid interface

MediumUVM ComponentsSystemVerilog

Implement a passive UVM monitor for a single-beat ready/valid interface. Publish exactly one transaction for each observed handshake and remain safe across reset and unknown control values.

Reviewed example

Work through one case

Input
successive samples: valid=1 ready=0; valid=1 ready=1 data=A; valid=X ready=1
Expected output
publish exactly one fresh transaction carrying A; report the unknown valid control

The passive monitor observes only known-high handshakes and neither a stall nor an unknown control creates an analysis transaction.

What to cover

Requirements

  1. Sample through a monitor clocking block and publish only when valid and ready are both known-high.
  2. Flush or ignore observations while reset is not known-deasserted.
  3. Report X or Z on handshake controls and on payload sampled during an accepted beat.
  4. Construct the analysis port and publish a fresh transaction object for every accepted beat.
Continue practicing
UVM ComponentsDrive a ready/valid interface correctlyUVM ComponentsReassemble interleaved transactions by IDAssertions and FormalReady-valid protocol assertions