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Hardware interview practice

Drive a multi-beat ready/valid transaction

MediumUVM ComponentsSystemVerilog

Expand one logical sequence item containing a queue of data beats into a ready/valid burst. Support backpressure, an accurate last flag, and optional idle bubbles between accepted beats.

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Reviewed example

Work through one case

Input
logical item beats=[A,B]; A handshakes; insert one idle bubble; present B with ready=0 then ready=1
Expected output
accepted burst=A then B; last=0 on A and last=1 held with B through its stall; item_done once

The beat index advances only on handshakes, and an optional bubble occurs before valid is reasserted for the final beat.

What to cover

Requirements

  1. Do not advance the beat index until the current beat handshakes.
  2. Assert last only for the final beat and hold it stable with the data while stalled.
  3. Insert a bubble only while valid is low; never ignore a possible handshake after asserting valid.
  4. Call item_done() once for the complete logical transaction, not once per physical beat.
  5. Reject an empty beat queue as an invalid burst item.
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UVM ComponentsDrive a ready/valid interface correctly→UVM ComponentsBuild a reset-responsive nonblocking driver→Functional CoverageCover handshakes and backpressure→
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