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Hardware interview practice

Cover handshakes and backpressure

MediumFunctional CoverageSystemVerilog

Create a UVM coverage subscriber for completed ready/valid transactions. Cover operation type, burst length, stall duration, errors, and a small set of meaningful interactions.

Reviewed example

Work through one case

Input
completed monitor transactions: READ len=1 stall=0 ok; WRITE len=16 stall=3 error; READ len=4 stall=8 ok
Expected output
hits include zero/short/long stall bins, boundary lengths 1 and 16, READxzero-stall, WRITExshort-stall, and WRITExerror

Only completed handshakes are sampled; the focused crosses capture operation/stall and operation/error behavior without crossing every field.

What to cover

Requirements

  1. Sample observed completed transactions from a monitor, not attempted driver items.
  2. Bin zero, short, and long stalls and include boundary burst lengths.
  3. Cross only interactions tied to a verification goal, such as operation by stall class and error by operation.
  4. Keep coverage separate from scoreboard checking and stimulus generation.
Continue practicing
Reference ModelsVerify a balanced-sequence enumeratorArbitersDesign a four-request arbiter verification environmentUVMBuild a FIFO UVM testbench