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Hardware interview practice

Detect overlapping 1011 sequences

MediumFSMsSystemVerilog

Design a serial detector for the pattern 1011 with overlap enabled. Assert match in the cycle that the final bit is accepted, and provide a bus functional model (BFM) check based on a sliding-window model rather than duplicating the FSM.

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Reviewed example

Work through one case

Input
accepted bits=[1,0,1,1,0,1,1] with arbitrary valid gaps
Expected output
match pulses on accepted bits 4 and 7

The sliding accepted-bit windows are 1011 at both endpoints in 1011011; valid gaps hold state and do not create positions.

What to cover

Requirements

  1. Sample one input bit whenever valid_in is high and hold state across valid gaps.
  2. Detect both occurrences in 1011011.
  3. Assert match only for a valid final bit and for one cycle per occurrence.
  4. The checker must compare against the last four accepted bits and preserve a short failure trace.
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