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Hardware interview practice

Cross a request between powered voltage domains

HardLow-Power DesignSystemVerilog

Design a reliable request crossing from a switchable 0.8 V domain A to an always-on 1.0 V domain B with unrelated clocks. A may power down only after every accepted request is acknowledged.

Starting point

Question code

// A: a_clk, a_rst_n, a_power_good, a_req, a_req_ready
// B: b_clk, b_rst_n, b_req_pulse
// Internal request and acknowledge levels cross in opposite directions.
Reviewed example

Work through one case

Input
A accepts one request, then the power controller asks A to shut down before B acknowledges
Expected output
Shutdown waits; B receives one pulse; acknowledgment returns; request drops; only then may isolation and power-off occur

The held level handshake prevents pulse loss and gives power control a definite idle state.

What to cover

Requirements

  1. Use a four-phase request/acknowledge level handshake and generate exactly one B-domain pulse per accepted request.
  2. Level-shift A-to-B and clamp the request to inactive before A powers off.
  3. Block shutdown until the handshake is idle; keep ready low during power loss and recovery.
  4. Synchronize both crossing levels and constrain unrelated clocks appropriately while preserving CDC-specific checks.
Continue practicing
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