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Hardware interview practice

Compare synchronous and asynchronous reset

EasyRTL DesignSystemVerilog

Which statement correctly compares synchronous and asynchronous reset behavior?

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Answer choices

  1. A. A synchronous reset changes state only on an active clock edge; an asynchronous reset can assert without a clock edge.
  2. B. An asynchronous reset can never cause recovery or removal problems.
  3. C. A synchronous reset works even when its clock is stopped.
  4. D. Both reset styles synthesize identically in every standard-cell library.
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