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Hardware interview practice

Identify an asynchronous-reset recovery violation

EasyClock and Reset DomainsSystemVerilog

A flip-flop library requires 80 ps recovery. Asynchronous reset deasserts 30 ps before the next active clock edge. Which conclusion is correct?

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Answer choices

  1. A. Only removal applies to reset deassertion before a clock edge, so no recovery check exists.
  2. B. The violation can be fixed by making reset assertion slower while leaving deassertion timing unchanged.
  3. C. Recovery passes by 50 ps because 80-30 is positive slack.
  4. D. Recovery fails by 50 ps; reset release should be synchronized or moved earlier so the deassertion-to-edge interval is at least 80 ps.
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