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Hardware interview practice

Check hold while stalled

EasyTemporal ChecksSystemVerilog

Given the previous cycle's ready/valid state and the current valid and payload values, return 1 when the transfer obeys the stall rule. After a stalled cycle, valid must remain asserted and the payload must stay unchanged.

Two sampled ready-valid edges showing a stalled transfer creating an obligation to hold valid and the payload at the next edge.
Read the obligation from the previous sampled edge, then check valid and payload at the current edge.
Reviewed example

Work through one case

Input
previous cycle: valid=1, ready=0, payload=0x55; current cycle: valid=1, ready=1, payload=0x56
Expected output
legal=0

The previous cycle created a hold obligation. The payload must remain 0x55 on the next sample even though ready is now high.

What to cover

Requirements

  1. Use the previous cycle to decide whether a hold obligation exists.
  2. Require current valid and use case equality for the four-state payload.
  3. Return legal when the previous cycle was not stalled.
Continue practicing
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