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Hardware interview practice

Detect X or Z in valid data

EasyVerification UtilitiesSystemVerilog

Report an error whenever a valid 32-bit data value contains any X or Z bit.

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Reviewed example

Work through one case

Input
cycle 4: valid=1,data contains bit X; cycle 5: valid=0,data contains bit Z
Expected output
error at cycle 4 only

Four-state detection flags the accepted unknown value, while invalid-cycle payload is deliberately ignored.

What to cover

Requirements

  1. Check only when valid is asserted.
  2. Detect both X and Z.
  3. Use four-state semantics.
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