Virtual memory
Translate, protect, and share physical memory.
Each process sees a private, contiguous virtual address space. The operating system owns mappings; the MMU enforces them on every instruction fetch, load, and store.
Protection
Per-page read, write, execute, privilege, and validity bits block unauthorized access.
Contiguous view
Virtual pages map onto fragmented physical frames without changing program addresses.
Demand and sharing
Pages can be created on demand, swapped to storage, shared, or privately copied on write.
Virtual pages and physical frames have equal size. The OS stores page-table entries in memory; a hardware or software walker follows the hierarchy from a per-process root to a leaf PTE. The leaf supplies the PPN, permissions, accessed/dirty state, and validity.
Each nine-bit index selects one of 512 entries. With eight-byte PTEs, one level's 512 entries occupy exactly one 4 KiB page. The 12-bit offset never participates in the walk and is copied unchanged into the physical address.
Virtual-address journey
Trace translation separately from the data access.
CPU issues a virtual address
VPN | page offsetThe page offset is already final. Only the virtual page number needs translation.
TLB miss
A miss is not necessarily a fault.
The walker reads page-table levels. A valid leaf refills the TLB and retries the access. An absent, invalid, or disallowed mapping raises a page fault. The OS may allocate a page, fetch it from storage, update the PTE, and restart the instruction.
Process protection
Check permission before touching data.
The TLB caches translation and permission state. Address-space identifiers prevent mappings from different processes from matching accidentally. Privilege and R/W/X checks occur before the cache can architecturally modify memory.
Interview diagnosis
Three misses, three different meanings.
| Event | What is absent | Normal next action | Architectural visibility |
|---|---|---|---|
TLB miss | A cached translation | Walk the page table, refill the TLB, retry | Usually a hidden performance event |
Page fault | A valid or permitted mapping | Enter the OS; allocate, load, reject, or update policy | Precise exception at the faulting instruction |
Cache miss | The translated data line | Fetch from the next memory-hierarchy level | Normally hidden unless a machine error occurs |
TLB coherence
Changing a PTE is only the first half of the update.
Private TLBs may retain stale permissions or a stale frame number. The OS must complete a coordinated shootdown before reusing the frame or trusting the new policy.
- 1
Lock the mapping and update or invalidate the page-table entry.
- 2
Issue inter-processor interrupts to cores that may cache the mapping.
- 3
Each target invalidates the matching TLB entry and executes required barriers.
- 4
Targets acknowledge; the initiating core can safely continue and reclaim resources.
Large and huge pages
Multiply TLB reach.
One TLB entry maps 2 MiB or 1 GiB instead of 4 KiB, reducing TLB misses and page-walk traffic for large, contiguous working sets.
- Memory utilization: internal fragmentation wastes the unused portion of a large page.
- OS management: contiguous physical allocation is harder and may require compaction.
- Operational cost: promotion, demotion, copy-on-write, migration, and swapping move more data.
- Granularity: protection and sharing decisions apply to a larger region.
Put it into practice
Explain the mechanism. Test your reasoning.
Use the experiment above to support your answer, then apply the idea in the question bank.
Continue the learning path
Next: Performance calculations
Work the quantitative problems with explicit hit-rate denominators, timing assumptions, units, and reproducible intermediate steps.