Instruction set architecture
The contract software sees.
An ISA defines program-visible behavior. Microarchitecture decides how a particular processor fulfills that contract.
Instruction set
The opcodes, encodings, and operations the processor can execute.
Visible registers
General-purpose and special registers software can name and manipulate.
Addressing modes
Immediate, register-relative, PC-relative, and other ways to identify operands.
Data types
Supported widths and formats, such as bytes, words, integers, and floating point.
RISC
Regular operations, pipeline-friendly control.
- Smaller set of simpler instructions
- Often fixed-length encodings
- Explicit load/store memory operations
- More sequencing responsibility for compilers
CISC
Expressive instructions, more complex decode.
- Larger and more varied instruction repertoire
- Often variable-length encodings
- Some instructions combine memory and computation
- Complex work may be translated into internal micro-operations
End-to-end system map
Follow one load from instruction bits to returned data.
The ISA defines what LW means. The pipeline calculates its virtual address, translation supplies a physical address, the hierarchy locates the line, and WB makes the loaded value visible in the destination register.
Classic datapath
Overlap work without changing program meaning.
A classic MIPS-style pipeline partitions instruction work across five stages. Pipeline registers hold each instruction's control and data between stages.
Instruction fetch
Read the instruction at the program counter and choose the next PC.
Decode and register read
Decode the opcode, identify operands, and read the register file.
Execute
Run the ALU, compare a branch, or calculate an effective address.
Memory
Access the data cache for a load or store.
Write back
Commit an ALU or load result into the architectural register file.
Control signals travel with the instruction. Forwarding paths return fresh EX or MEM results to ALU inputs; branch resolution redirects the PC; WB closes the loop at the register file.
Interactive pipeline timeline
See overlap, bubbles, bypasses, and flushes cycle by cycle.
Independent instructions enter on consecutive cycles. Latency remains five cycles, but steady-state throughput reaches one completed instruction per cycle.
No dependency or resource conflict requires a bubble.
Pipeline hazards
When the next instruction cannot safely advance.
A hazard is a timing condition, not automatically a bug. The interlock, bypass, and recovery machinery must preserve architectural behavior.
Structural hazard
Two stages request hardware that cannot serve both in the same cycle.
Resolve with replication, multi-porting, arbitration, or a stall.Data hazard
A consumer reaches its operand-use point before the producer's result is available.
Forward when timing permits; otherwise interlock and inject a bubble.Control hazard
A branch or exception makes already-fetched instructions potentially incorrect.
Predict to stay busy, then flush and redirect when the guess is wrong.ADD r1, r2, r3
SUB r4, r1, r5LW r1, 0(r2)
ADD r3, r1, r4The ADD result exists after EX and can bypass to the next EX. The load result exists only after MEM, so an adjacent consumer needs one bubble in this five-stage timing model.
Register-file edge case
Instruction i writes while i+3 reads.
The ISA only requires the SUB to observe the ADD result. The register-file circuit decides whether that same-cycle read is write-first, read-first, or unsupported. A half-cycle convention or WB-to-ID bypass avoids a bubble; a read-first single-port implementation must interlock.
Interview reasoning
Locate the boundary before naming the fix.
- 1
Produce: At which stage and edge does the value or decision become valid?
- 2
Consume: At which stage and edge must the younger instruction sample it?
- 3
Transport: Is there a bypass or port connecting those two points in time?
- 4
Hold: Which pipeline registers freeze, and where is the bubble inserted?
- 5
Recover: Which younger side effects must be killed after a redirect?
Reason aloud
Questions that expose the timing model
Why can forwarding not completely remove a load-use hazard?+
A load receives its data at the end of MEM, while the following instruction needs the operand at the beginning of EX in that same cycle. The value arrives after the consumer's sampling boundary, so the pipeline stalls once and then forwards it.
What this tests: Stage timing, not merely the definition of a RAW dependency.How do pipeline latency and throughput differ?+
Latency is the time for one instruction to pass from IF through WB. Throughput is the completion rate across many overlapped instructions. A five-stage pipeline can retain five-cycle latency while approaching one instruction per cycle after filling.
What this tests: Whether the candidate separates per-item delay from system rate.Can ID read and WB write the same register in one cycle?+
Instruction i can write r1 in WB while instruction i+3 reads r1 in ID. This is not an architectural WAR hazard. It is a same-cycle register-file timing or port conflict if the implementation returns old data or cannot perform both operations. A write-first array, first-half write plus second-half read, or explicit WB-to-ID bypass removes the stall; otherwise ID waits one cycle.
What this tests: The difference between an ISA dependency and a microarchitectural resource constraint.Where does a one-port unified L1 cache create a structural hazard?+
When a load or store reaches MEM, a younger instruction simultaneously needs the only port for IF. The processor must choose one request, normally the older data access, and hold the PC and fetch stage until the port becomes free.
What this tests: Resource occupancy across stages.Pipeline performance
2.5 GHz benchmark
40% ALU, 25% branch, 20% load, 15% store.