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Part 1 · Values and layout

Values, objects, and fixed layout

Separate value domain from driver semantics, then read packed and unpacked dimensions as an explicit layout contract.

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  1. Q0034-state data typesSystemVerilog · EasyPractice
  2. Q2884-state equalitySystemVerilog · EasyPractice
  3. Q647Nets and variablesSystemVerilog · EasyPremium
  4. Q557Match uninitialized values to their data typesSystemVerilog · EasyPremium
  5. Q558Compare values safely with X and ZVerification Utilities · EasyPremium
Complete question directoryFilter every stable practice link by mechanism.5 questions
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  1. Q0034-state data typesSystemVerilog · EasyPractice
  2. Q2884-state equalitySystemVerilog · EasyPractice
  3. Q647Nets and variablesSystemVerilog · EasyPremium
  4. Q557Match uninitialized values to their data typesSystemVerilog · EasyPremium
  5. Q558Compare values safely with X and ZVerification Utilities · EasyPremium

01 · Value systems and objects

Separate what a value can represent from how an object is driven.

The fastest route to correct SystemVerilog is to make two decisions independently: the value domain of the data and the object semantics of the name that carries it.

Rule to say firstChoose 2-state versus 4-state for observability, then choose net versus variable for connectivity and ownership; never use logic as shorthand for “wire plus reg.”

Two independent axes

Value domain is not object kind

Value domainObject kindVariableRetains a value; one procedural owner is the normal contract.NetRepresents connectivity and resolves its active drivers.
4-state0 · 1 · X · Z remain observable
2-stateOnly 0 · 1 remain observable
  1. 014-state variablelogic

    Stores 0, 1, X, or Z; normally one procedural owner.

  2. 024-state netwire logic

    Carries resolved values from continuous or module drivers.

  3. 032-state variablebit

    Stores binary values; assigning X/Z collapses diagnostic state.

  4. 042-state netwire bit

    A resolved connection with a 2-state data type; contention information is coerced at the declared boundary.

4-state variablelogic

Stores 0, 1, X, or Z; normally one procedural owner.

int
32-bit · 2-state
A compact simulation value when X/Z observability is not required.
integer
32-bit · 4-state
A legacy 4-state integral type; it is not an alias for int.
logic
4-state variable type
Object context still determines whether the declaration is a net or variable.

Read declarations in two passes: first the data type and value domain, then the object kind and driver model.

01

Observe

List the values that must remain observable, the number of drivers, and whether resolution is part of the interface contract.

02

Decide

Use 4-state logic where X/Z exposes initialization, contention, or tri-state behavior; use 2-state types where those states are intentionally collapsed.

03

Failure

A 2-state conversion can hide an X, while a variable with multiple procedural writers creates an ownership error rather than net resolution.

04

Prove

Lint driver ownership, assert knownness at protocol boundaries, and test conversions with 0, 1, X, and Z—not only nominal binary values.

The four-state model is diagnostic information

X can mean uninitialized, conflicting, unknown, or intentionally pessimistic data; Z represents high impedance on resolved connectivity. Those meanings are valuable at control and interface boundaries. A 2-state assignment cannot preserve them, so conversion is a deliberate loss of information.

Core integral families
TypeWidthStatesDefault signednessTypical use
bituser-shaped2unsignedCompact models and flags
logic / reguser-shaped4unsignedRTL state and observability
byte82signedCharacters and small arithmetic
shortint162signedCompact arithmetic
int322signedLoop variables and models
integer324signedLegacy 4-state arithmetic
longint642signedWide arithmetic

Nets resolve; variables retain

A net represents connectivity and may combine multiple drivers according to its net type. A variable stores the last assignment and should have a clear writer. In ports, spell out both object and data type when ambiguity would affect ownership.

  • Use wire logic for an explicitly four-state net and logic for a procedurally assigned variable.
  • Continuous assignments and module outputs naturally drive nets; procedural blocks assign variables.
  • wand and wor encode wired resolution, but ordinary datapaths should not rely on accidental multi-driver resolution.
  • Treat signedness as part of the interface: unsized literals and mixed signed expressions can change extension and comparison behavior.
Make connectivity and storage explicitsystemverilog
wire logic resolved_irq;
logic      sampled_irq;
bit        model_enable;

assign resolved_irq = irq_a;
assign resolved_irq = irq_b; // net resolution is intentional

always_ff @(posedge clk) begin
  sampled_irq <= resolved_irq; // one procedural owner
end

assert property (@(posedge clk) model_enable |-> !$isunknown(sampled_irq));

Explain it out loud

Interview reasoning checkpoints

Strong answer

No. logic is a four-state variable data type. A declaration can still be a net or a variable depending on syntax and context, and that object kind controls driving and resolution.

Reason it through
  1. Identify the data domain: four-state logic preserves X and Z.
  2. Identify the object: a net models connectivity; a variable models stored procedural state.
  3. Check ownership: multiple procedural writers are not made safe by changing reg to logic.
Interviewer lens

A strong answer separates data type from object kind and mentions driver ownership.

Common trap

Saying “logic can always be driven from anywhere” ignores port defaults, continuous drivers, and single-writer intent.

Strong answer

Both are 32-bit signed integral types, but int is 2-state and integer is 4-state. Choose based on whether X/Z observability is part of the model.

Reason it through
  1. A four-state source assigned to int loses X/Z information.
  2. That loss may be useful for performance in a reference model but dangerous at a verification boundary.
  3. Use explicit casts and knownness assertions when crossing the domains.
Interviewer lens

The key distinction is state domain, not width or signedness.

Common trap

Calling int four-state because logic is commonly used beside it.

02 · Fixed arrays and dimensionality

Packed dimensions shape bits; unpacked dimensions shape elements.

Range placement changes arithmetic, slicing, assignment compatibility, memory inference, and the order in which bits travel through a conversion.

Rule to say firstRead dimensions from the identifier outward for elements and from the type inward for contiguous bits; never infer byte order from an ascending or descending declaration alone.

Shape before syntax

One declaration, two coordinate systems

lane[0]
byte 1byte 0
Packed left-to-right significance follows declared ranges.
lane[1]
byte 1byte 0
lane[2]
byte 1byte 0
lane[3]
byte 1byte 0
  1. 01Packed plane[1:0][7:0]

    Sixteen contiguous bits; integral operators and slices apply.

  2. 02Element planelane [0:3]

    Four independently indexed packed elements.

  3. 03Total storage64 bits

    $bits reports the complete fixed-size object.

Packed plane[1:0][7:0]

Sixteen contiguous bits; integral operators and slices apply.

Packed
Integral
Supports arithmetic, reduction, concatenation, and part-selects.
Unpacked
Elements
Supports array methods and natural memory-style indexing.
Range direction
Index convention
It does not by itself define memory endianness.

A multidimensional declaration is a layout contract. Name each axis before writing a cast, slice, port, or DPI adapter.

01

Observe

Mark every packed dimension before the identifier and every unpacked dimension after it, including typedef-expanded dimensions.

02

Decide

Use packed arrays for vectors and fields that participate in integral operations; use unpacked arrays for independently indexed elements or memories.

03

Failure

Treating an unpacked byte array as a word creates assignment errors or an unintended reordering at the adapter.

04

Prove

Check $bits, $dimensions, $left, $right, $low, $high, and explicit boundary examples with non-symmetric values.

Packed versus unpacked is a semantic choice

Packed arrays form one contiguous integral value. Unpacked arrays are collections of values. Both can have many dimensions, and typedefs can hide part of the shape, so APIs should document element type and dimension order.

The identifier divides bit dimensions from element dimensionssystemverilog
typedef logic [7:0] byte4_t [0:3];

logic [1:0][7:0] lane [0:3];
byte4_t bytes;

initial begin
  assert ($bits(lane) == 64);
  lane[2][1] = 8'hA5;
  lane[2][0][3 +: 4] = 4'hC;
end

Query the declaration instead of duplicating it

Array query functions make generic code resilient to range direction and typedef changes. For a mixed array, dimension numbers enumerate unpacked dimensions first and then packed dimensions, so name the queried dimension instead of assuming a memory layout.

  • For logic [7:0] lane [0:3], dimension 1 is unpacked [0:3] and dimension 2 is packed [7:0].
  • $increment reports range direction: +1 for a descending range and -1 for an ascending range. Subtract it from an index to move from $left toward $right.
  • Use $dimensions and $unpacked_dimensions to validate an adapter before applying a dimension-specific query.
Useful shape queries
QueryAnswersReview use
$bits(expr)Total packed storage in bitsSerialization and DPI widths
$dimensions(expr)Total dimensionsGeneric shape checks
$unpacked_dimensions(expr)Unpacked dimensionsMemory and array adapters
$size(expr, n)Elements in dimension nBounds-independent loops
$left / $rightDeclared endpointsDirection-preserving traversal
$low / $highNumeric endpointsOrder-independent range checks
$increment(expr, n)+1 descending, -1 ascendingSubtract it to move from $left to $right

Explain it out loud

Interview reasoning checkpoints

Strong answer

Packed dimensions create one contiguous integral value; unpacked dimensions create a collection of elements. That difference controls operators, slicing, assignment compatibility, and often implementation intent.

Reason it through
  1. Locate dimensions relative to the identifier.
  2. Ask whether the design needs bit arithmetic or element-oriented storage.
  3. Make any crossing explicit with loops, concatenation, assignment patterns, or streaming.
Interviewer lens

Use a concrete declaration and explain where its bits and elements live.

Common trap

Reducing the distinction to syntax without explaining operations or layout.

Strong answer

No. Those ranges define index direction and significance within a SystemVerilog object. Memory byte order is a separate interface convention that must be specified at the boundary.

Reason it through
  1. Range direction tells which index is left and right.
  2. Endianness tells how multi-byte values map to addressed bytes.
  3. Use an asymmetric test word such as 32'hA53C1B7E to validate the adapter.
Interviewer lens

The answer should separate language indexing from architecture-level byte order.

Common trap

Assuming a range direction automatically defines memory layout.