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Hardware interview practice

XNOR from one 2-to-1 mux

EasyRTL DesignSystemVerilog

A small control block may use one 2-to-1 mux and one inverter, but no XOR or XNOR operator. Write synthesizable SystemVerilog for the XNOR function using that structure.

Starting point

Question code

input logic a, b;
output logic y;
Reviewed example

Work through one case

Input
a=0 and b=0.
Expected output
y=1.

With a selecting the mux's zero input, the mux chooses ~b; because b is zero, the selected value is one, matching XNOR.

What to cover

Requirements

  1. For 0/1 inputs, y must equal one exactly when a and b are equal.
  2. Use a as the mux select, b on the select-one input, and the inverse of b on the select-zero input.
  3. Do not use ^, ~^, or == in the implementation of y.
  4. Use combinational, synthesizable logic with no inferred storage.
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