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Enabled modulo-five counter

EasyRTL DesignSystemVerilog

A controller cycles through five slots only when enable is asserted. Implement the modulo-five counter in synthesizable SystemVerilog.

Starting point

Question code

input logic clk, rst_n, enable;
output logic [2:0] count;
output logic wrap;
Reviewed example

Work through one case

Input
Before a rising edge: rst_n=1, count=3, enable=1.
Expected output
After the edge: count=4 and wrap=0.

The enabled counter increments because the pre-edge value is below the terminal count of four; wrap remains low because no 4-to-0 transition occurred.

What to cover

Requirements

  1. On an enabled rising edge, count advances 0,1,2,3,4,0; on a disabled edge it holds.
  2. wrap pulses for exactly the enabled edge that changes count from 4 to 0.
  3. When rst_n=0 at a rising edge, set count=0 and wrap=0 regardless of enable.
  4. For all other enabled edges, wrap is zero and count never takes a value above 4.
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