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Hardware interview practice

$past and nonblocking assignment (NBA) sampling

HardTemporal ChecksSystemVerilog

After the first usable history sample, how should this property behave when d is known and stable around each posedge and q has no other drivers?

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Question code

always_ff @(posedge clk) q <= d;
assert property (@(posedge clk) q == $past(d));
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Answer choices

  1. A. It should pass: sampled q reflects the prior edge's NBA update, matching prior sampled d
  2. B. It should fail every cycle because the assertion samples q after the current NBA
  3. C. It is a race and may pass or fail depending on process order
  4. D. It compares q with d from two edges earlier
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