Skip to question
asic.fyi

Hardware interview practice

Sequence local variables

HardTemporal ChecksSystemVerilog

What does local variable t accomplish, and what does this sequence still not guarantee?

Starting point

Question code

typedef logic [7:0] tag_t;
tag_t req_tag, rsp_tag;

sequence tagged_response;
  tag_t t;
  (req, t = req_tag) ##[1:3] (ack && rsp_tag == t);
endsequence
Choose one

Answer choices

  1. A. It forces the design signal tag to stay constant globally
  2. B. It captures req_tag per attempt and checks for an ack with the same-width rsp_tag 1 to 3 clocks later, but alone does not enforce one-to-one matching when tags are reused
  3. C. It delays assignment to tag until ack
  4. D. It is shared by all assertion instances and therefore permits only one outstanding request
Continue practicing
Temporal Checks$past and nonblocking assignment (NBA) samplingTemporal ChecksVacuity