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Hardware interview practice

Trade ICG granularity for fanout and timing

MediumLow-Power DesignSystemVerilog

What is the main tradeoff when one shared ICG is moved upstream to gate many flops?

Choose one

Answer choices

  1. A. It eliminates enable timing checks.
  2. B. It guarantees zero skew.
  3. C. It can reduce ICG count and gate more clock load when enables match, but increases fanout, placement, and enable-timing burden and loses fine-grained gating.
  4. D. It increases ICG count while reducing fanout.
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