Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Scale distributed-wire delay with length

Hardware interview practice

Scale distributed-wire delay with length

EasyPhysical DesignSystemVerilog

An unbuffered uniform 100 um wire has 100 ps delay. Under a distributed RC model, approximately what delay should a 200 um version have?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. 100 ps
  2. B. 200 ps
  3. C. 400 ps
  4. D. 800 ps
Continue practicing

Related questions

Physical DesignTrade speed for leakage with multi-Vt cells→Physical DesignPredict opposite-direction crosstalk delay→Physical DesignRelieve localized routing congestion→
asic.fyi · Learn silicon end to end.info@asic.fyi