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Hardware interview practice

Top-down build traversal

EasyUVM ComponentsSystemVerilog

The agent reads is_active from config_db in its build_phase. Assuming no competing setting, what value does it read in this test?

Starting point

Question code

function void test::build_phase(uvm_phase phase);
  super.build_phase(phase);
  env = env_t::type_id::create("env", this);
  uvm_config_db#(uvm_active_passive_enum)::set(
      this, "env.agt", "is_active", UVM_PASSIVE);
endfunction
Choose one

Answer choices

  1. A. UVM_ACTIVE, because the set occurs after env is constructed
  2. B. UVM_ACTIVE, because config_db cannot store enum values
  3. C. UVM_PASSIVE, because child build_phase methods run only after the parent's build_phase returns
  4. D. The result is nondeterministic across simulators
Continue practicing
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