Skip to question and answer

Hardware interview practice

UVM build_phase vs. connect_phase

EasyUVM ComponentsMultiple choice

Which allocation of work follows normal UVM phase intent?

Answer choices

  1. A. Create all transactions in connect_phase and connect interfaces in report_phase
  2. B. Connect ports in build_phase and create children in run_phase
  3. C. Create child components in build_phase and connect their transaction-level modeling (TLM) ports in connect_phase
  4. D. Create child components in final_phase because the hierarchy is complete

Concise answer

The answer and the key reason

Create child components during `build_phase`, then bind their TLM connections during `connect_phase`. Construction must finish before connections are made, so every required port, export, and child instance exists when the testbench wiring is established.

Deeper explanation

Work through the implementation and tradeoffs

`build_phase` is where a component reads construction-time configuration and creates its children, normally through factory `create` calls. Its top-down traversal lets a parent establish settings before a child executes its own build logic. By the end of this phase, the intended testbench hierarchy should be present.

`connect_phase` follows construction and is used to join TLM ports, exports, implementations, analysis paths, and related handles. Because the hierarchy already exists, connections can refer safely to both endpoints. Building children in a runtime or final phase is too late for normal topology setup, while connecting them prematurely can reference objects that have not yet been created.

What to remember

  • Build creates children
  • Connect binds endpoints
  • Construction precedes wiring

Practice the complete prompt

Explain it first, then compare the reviewed solution.

Open this exact question in the practice bank to attempt it, check your reasoning, and access the full member solution.Practice this question

Keep practicing

UVM Componentsuvm_object vs. uvm_componentUVM ComponentsHow UVM Phase Objections WorkUVM ComponentsHow UVM Factory Type Overrides Work