Hardware interview practice
Time Two Related FPGA Clock Domains
One MMCM generates a phase-aligned 100 MHz clock and a phase-aligned 50 MHz clock from the same input. Both generated clocks and their relationship are guaranteed by the device clocking resource. How should ordinary register crossings between these domains be handled?
Choose one
Answer choices
- A. Declare the clocks asynchronous solely because their frequencies differ and false-path every crossing between them.
- B. Use a two-flop synchronizer on every multi-bit bus and ignore setup/hold timing because synchronizers guarantee coherent words.
- C. Define both generated clocks from their common source and let STA analyze the legal launch/capture edge pairs; use dedicated clock routing and add synchronization only for signals whose functional protocol or phase relationship is actually asynchronous.
- D. Route the 50 MHz clock from a fabric counter bit and omit generated-clock constraints because it is an exact divide by two in simulation.