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Hardware interview practice

Choose the direct fix for a hold violation

EasyTimingSystemVerilog

Static timing reports a hold violation on a same-edge register path. Which change is the usual direct repair when the clock period must stay fixed?

Choose one

Answer choices

  1. A. Reduce the clock frequency.
  2. B. Add delay to the data path that is arriving too early.
  3. C. Replace the launch flop with a faster cell.
  4. D. Remove buffers from the data path.
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