Hardware interview practice
Why UVM Uses SystemVerilog Virtual Interfaces
Why is a virtual interface commonly placed into a class-based driver's configuration?
virtual bus_if.master vif;Answer choices
- A. It copies all interface signals into class properties
- B. It creates a new interface instance for every transaction
- C. It converts 4-state interface signals to 2-state class variables
- D. It gives the class a handle to a particular interface instance without hard-coding hierarchy
Concise answer
The answer and the key reason
Deeper explanation
Work through the implementation and tradeoffs
An HDL interface belongs to the static design hierarchy, whereas a verification class is created dynamically. The class therefore uses a virtual-interface variable as a reference to the existing interface rather than attempting to instantiate or copy it. Through that reference, driver methods can read clocking information and drive protocol signals.
The test or environment can place the desired handle in configuration before the driver builds, and the driver retrieves it without knowing the top-level instance path. That separation improves reuse across benches and agent instances. Typing the variable as `virtual bus_if.master` also limits access to the master-facing members and directions.
What to remember
- References an existing interface
- Configuration removes hierarchy coupling
- Modport typing limits access
Practice the complete prompt