Hardware interview practice
SystemVerilog Clocking Blocks Explained
What timing intent is expressed by this clocking block?
clocking cb @(posedge clk);
default input #1step output #0;
input q;
output d;
endclockingAnswer choices
- A. q is sampled one full clock period earlier and d one period later
- B. q is sampled one simulator time step before the edge, and d is driven with zero skew at the clocking event
- C. q and d are both changed in the preponed region
- D. The declaration inserts synthesizable delays into the DUT
Concise answer
The answer and the key reason
Deeper explanation
Work through the implementation and tradeoffs
Each positive edge of `clk` establishes the clocking event. The default input skew applies to `q`, so `#1step` takes its sampled value immediately before that event. The default output skew applies to `d`, and `#0` schedules the clocking-block drive without moving it to a later simulation time.
Separating the observation and drive instants helps a testbench avoid races with design processes triggered by the same clock edge. Code should access these signals through the clocking block to receive those semantics. The declaration affects simulator scheduling at the verification boundary; it does not change the DUT’s clock-to-output behavior or synthesize delay elements.
What to remember
- `#1step` samples before the edge
- `#0` drives at event time
- Clocking skew is testbench timing
Practice the complete prompt