Hardware interview practice
SystemVerilog solve before Constraint Semantics
How does solve a before b change this randomization?
rand bit a;
rand bit [1:0] b;
constraint c {
(a == 0) -> (b == 0);
solve a before b;
}Answer choices
- A. It changes the legal solutions and forces a to 0
- B. It leaves the legal solutions unchanged but makes P(a=0) one half rather than one fifth
- C. It makes P(a=0) one fifth rather than one half
- D. It is illegal because implication and solve before cannot appear together
Concise answer
The answer and the key reason
Deeper explanation
Work through the implementation and tradeoffs
The implication permits only `b=0` when `a=0`; when `a=1`, all four two-bit values of `b` are allowed. That creates one tuple whose first field is zero and four whose first field is one. Under the prompt’s equal-tuple model and without ordering, the lone zero tuple receives one fifth of the probability.
With `a` solved first, its legal values zero and one are selected at that stage with equal probability. The later conditional choice for `b` has one option after zero and four options after one, but it does not retroactively bias `a`. The directive changes sampling distribution, not satisfiability or the set of permitted tuples.
What to remember
- Five legal tuples remain
- Ordering changes marginal probability
- `solve before` is not a filter
Practice the complete prompt