Skip to question and answer

Hardware interview practice

SystemVerilog Soft Constraints Explained

MediumConstraintsMultiple choice

What happens when randomize is called?

Question code
class C;
  rand int x;
  constraint defaults { soft x inside {[0:9]}; }
endclass
C c = new;
initial assert(c.randomize() with { x == 20; });

Answer choices

  1. A. Randomization fails because 20 is outside 0 through 9
  2. B. The inline constraint is ignored
  3. C. Randomization succeeds with x clamped to 9
  4. D. Randomization succeeds with x equal to 20

Concise answer

The answer and the key reason

Randomization succeeds with `x` equal to 20. The class range is marked `soft`, so it behaves as a fallback preference. The inline equality is hard; when the two conflict, the solver discards the soft restriction rather than failing or clamping the result.

Deeper explanation

Work through the implementation and tradeoffs

A soft constraint supplies a default that remains active only when it can coexist with all applicable hard constraints. Here the inline `with` clause requires exactly 20, while the class-level preference would allow only 0 through 9. Because those sets do not overlap, the soft expression yields and the hard equality determines the value.

If `soft` were removed, both expressions would be mandatory and there would be no legal assignment, causing `randomize()` to return zero. Nothing in constrained randomization automatically clips 20 to 9, and the inline clause is not ignored. Soft constraints are therefore useful for reusable defaults that individual tests may intentionally replace.

What to remember

  • Soft means overridable default
  • Inline equality remains hard
  • No automatic value clamping

Practice the complete prompt

Explain it first, then compare the reviewed solution.

Open this exact question in the practice bank to attempt it, check your reasoning, and access the full member solution.Practice this question

Keep practicing

ConstraintsSystemVerilog Basic Constraint Interview QuestionConstraintsSystemVerilog dist Constraints ExplainedConstraintsSystemVerilog solve before Constraint Semantics