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Hardware interview practice

Stress a page-walk and cache race

MediumComputer ArchitectureSystemVerilog

A hardware page walker shares the data cache while software can update page tables under the architecture’s synchronization rules. Which verification scenario adds the most value?

Choose one

Answer choices

  1. A. Verify only TLB hits after boot.
  2. B. Race page-table updates and required invalidation with cache eviction/writeback, permission faults, and a walk in flight.
  3. C. Randomize page-table memory while a walk runs, without executing the required architecture synchronization.
  4. D. Disable both the cache and MMU for every page-table test.
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