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Hardware interview practice

Split a cache address

EasyComputer ArchitectureSystemVerilog

A 4 KiB cache is two-way set associative, has 32-byte lines, and uses 32-bit byte addresses. How many offset, index, and tag bits are used?

Choose one

Answer choices

  1. A. 5 offset bits, 7 index bits, and 20 tag bits.
  2. B. 5 offset bits, 6 index bits, and 21 tag bits.
  3. C. 5 offset bits, 6 index bits, and 32 tag bits.
  4. D. 6 offset bits, 5 index bits, and 21 tag bits.
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