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Select CDC structures for five signal classes

MediumDesign VerificationSystemVerilog

A subsystem has five crossings between unrelated source and destination clocks. Design the CDC plan and the structural checks for every crossing.

Starting point

Question code

A enable_level: one bit, stable for at least 3 destination cycles
B irq_event: one source-cycle pulse; at most 3 events may be outstanding
C count[7:0]: monotonically increments by at most one per source edge
D stream: 32-bit ready/valid data with sustained traffic
E rst_n: asynchronous external reset into the destination domain
Reviewed example

Work through one case

Input
Case 1: Issue two irq_event pulses before one destination edge
Case 2: Present a fourth event while three remain unconsumed
Case 3: Transfer words 10,11,12 through the asynchronous FIFO
Expected output
Case 1: the counted-event scheme produces two destination events
Case 2: the source contract is violated and the outstanding-count assertion fires
Case 3: each word is read exactly once and in order under any legal clock ratio

The shown result follows by applying this rule: Match the crossing method to semantics: stable level, lossless event, constrained counter, arbitrary stream, or reset. The cases also demonstrate this requirement: For E, assert reset asynchronously and deassert it through a destination-domain reset synchronizer; run CDC/RDC checks for reconvergence, coherency, reset release, and illegal direct use of stage one.

What to cover

Requirements

  1. Use a destination two-flop synchronizer for A, and do not edge-detect it until after synchronization if an event is needed.
  2. For B, increment a 2-bit modulo-4 source event counter, transfer its Gray code to the destination, and emit at most one pulse per destination cycle while a local consumed counter differs. Return the consumed counter's Gray code to the source and assert that irq_event is low whenever the modulo distance is already three; coordinated reset clears both counters.
  3. Register C as Gray code in the source, synchronize every Gray bit, constrain inter-bit skew, and decode only after synchronization; use an asynchronous FIFO for D.
  4. For E, assert reset asynchronously and deassert it through a destination-domain reset synchronizer; run CDC/RDC checks for reconvergence, coherency, reset release, and illegal direct use of stage one.
Continue practicing
Clock Domain CrossingMatch each signal type to a CDC techniqueClock and Reset DomainsSeparate related-clock timing from asynchronous CDCClock and Reset DomainsImplement a four-phase CDC event handshake