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Reset-aware driver design

MediumUVM ComponentsSystemVerilog

Which reset strategy gives the clearest behavior for an active driver?

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Answer choices

  1. A. Ignore reset in the driver because only the monitor needs it
  2. B. Assume reset automatically deletes every request and response in all UVM components
  3. C. Define how to stop pin activity, classify or complete an in-flight item, restore the sequencer handshake, and resume from a known interface state
  4. D. Call phase.drop_objection once per reset cycle regardless of who raised it
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