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Hardware interview practice

Phase jumping

MediumUVM ComponentsSystemVerilog

A runtime phase jumps backward from main_phase to reset_phase. Which design assumption is safest?

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Answer choices

  1. A. Tasks and component state are automatically reconstructed exactly as at time zero
  2. B. A jump changes report verbosity but not schedule control
  3. C. Only build_phase reruns, while runtime phases continue uninterrupted
  4. D. Affected phases may be terminated and re-entered, so phase code and cleanup must tolerate interruption and repeated execution
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