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Hardware interview practice

Reassemble interleaved transactions by ID

HardUVM ComponentsSystemVerilog

Extend a ready/valid monitor to reconstruct multi-beat transactions whose beats may interleave across transaction IDs. Publish only complete transactions.

Reviewed example

Work through one case

Input
accepted beats: id1=A0 last=0; id2=B last=1; id1=A1 last=1
Expected output
publish transaction id2=[B], then id1=[A0,A1]

Separate per-ID partial buffers allow id2 to complete between id1 beats without corrupting either assembly order.

What to cover

Requirements

  1. Maintain independent partial assembly state for each ID.
  2. Append a beat only on a valid/ready handshake and publish when that ID's last beat is accepted.
  3. Flush every partial transaction on reset.
  4. Assume at most one unfinished transaction per ID; state that a sequence tag is required otherwise.
Continue practicing
UVM ComponentsMonitor a ready/valid interfaceUVMMatch out-of-order responses by IDReference ModelsTrack named bin hits