Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/RAL set and update

Hardware interview practice

RAL set and update

EasyReference ModelsSystemVerilog

In UVM Register Abstraction Layer (RAL) code, what happens when software calls reg.set('h35) followed later by reg.update(status, .path(UVM_FRONTDOOR))?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. set immediately performs a bus write, and update only prints the value
  2. B. set changes desired state without accessing the DUT; update writes when the model determines an update is needed
  3. C. set changes only the mirror and update always performs a backdoor read
  4. D. Neither operation can affect a writable register
Continue practicing

Related questions

Reference ModelsRAL desired and mirrored values→Reference ModelsRAL mirror with checking→
asic.fyi · Learn silicon end to end.info@asic.fyi