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RAL desired and mirrored values

EasyReference ModelsSystemVerilog

In the UVM Register Abstraction Layer (RAL), what do desired and mirrored values represent?

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Answer choices

  1. A. Desired is the value the model wants in the DUT; mirrored is the model's current prediction of the DUT value
  2. B. Desired is always the reset value; mirrored is always the last randomized value
  3. C. Desired is frontdoor-only; mirrored is backdoor-only
  4. D. They are two names for the same immutable field
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