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RAL frontdoor and backdoor

EasyReference ModelsSystemVerilog

In the UVM Register Abstraction Layer (RAL), which distinction between frontdoor and backdoor register access is correct?

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Answer choices

  1. A. Frontdoor is read-only and backdoor is write-only
  2. B. Frontdoor uses the modeled bus/protocol path; backdoor accesses the hardware description language (HDL) implementation path without creating bus traffic
  3. C. Backdoor always consumes more bus cycles
  4. D. The two paths are synonyms in UVM 1.2
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