Hardware interview practice
Pulse on every adjacent pair of ones
A trace filter must mark every sample whose value and immediately preceding sample are both one; adjacent matches may overlap. Implement the one-bit history detector in synthesizable SystemVerilog.
Starting point
Question code
input logic clk, rst_n, bit_in;
output logic pair_pulse;Reviewed example
Work through one case
Input
After reset, sample bit_in values 0, 1, 1 on successive edges.Expected output
pair_pulse values are 0, 0, 1.Only the third sample is one while the saved immediately previous sample is also one, so it completes the adjacent pair.
What to cover
Requirements
- Sample bit_in on each rising edge and pulse when the current and previous sampled values are both one.
- Allow overlap, so input 111 produces pulses on the second and third samples.
- When rst_n is zero at a rising edge, clear the saved history and pair_pulse.
- pair_pulse is low on every sample that does not complete an adjacent pair.