Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Local repair for a hold violation

Hardware interview practice

Local repair for a hold violation

EasyTiming and STASystemVerilog

A same-cycle data path reaches the capture flip-flop 35 ps too early. Setup slack on that path is +140 ps. Which local change is the direct hold repair while retaining the same clock period?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Choose one

Answer choices

  1. A. Add at least 35 ps of delay to the data path, with margin, while rechecking setup slack.
  2. B. Increase the clock period until the hold slack becomes positive.
  3. C. Remove delay from the data path to make the transition cleaner at the capture pin.
  4. D. Replace the capture flip-flop with a faster one so data is captured sooner.
Continue practicing

Related questions

Timing and STACalculate a falling-to-rising half-cycle setup path→Timing and STAChoose coupled setup and hold ECOs→Timing & STAPair setup and hold multicycle constraints→
asic.fyi · Learn silicon end to end.info@asic.fyi