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Hardware interview practice

Nets and variables

EasySystemVerilogSystemVerilog

Two continuous assignments intentionally drive the same 4-state signal, and normal net resolution is required. Which declaration is appropriate?

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Question code

assign bus_ok = src_a;
assign bus_ok = src_b;
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Answer choices

  1. A. logic bus_ok;
  2. B. bit bus_ok;
  3. C. wire logic bus_ok;
  4. D. var logic bus_ok;
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SystemVerilog4-state data types→SystemVerilog4-state equality→
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