Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Maximum clock frequency from a setup path

Hardware interview practice

Maximum clock frequency from a setup path

MediumTimingPYTHON

For each setup path, positive skew means the capture clock arrives after the launch clock. Calculate the minimum clock period and maximum frequency using the given picosecond delays and uncertainty.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Starting point

Question code

Tmin = Tcq + Tcomb + Tsetup + uncertainty - capture_skew
Fmax_GHz = 1000 / Tmin_ps

P1 = (80, 620, 100, 60,  40)
P2 = (70, 500,  80, 50,   0)
P3 = (90, 700, 110, 40, -30)
// tuple order: Tcq,Tcomb,Tsetup,uncertainty,capture_skew
Reviewed example

Work through one case

Input
P3: Tcq=90, Tcomb=700, Tsetup=110, uncertainty=40, capture_skew=-30 ps
Expected output
Tmin=970 ps; Fmax=1.031 GHz

Subtracting -30 adds 30 ps to the requirement: 90+700+110+40+30=970 ps.

What to cover

Requirements

  1. Apply the formula independently to each path.
  2. Treat negative capture skew as additional required period because the formula subtracts it.
  3. Keep every delay in picoseconds and report frequency in GHz.
  4. Report period as integer picoseconds and frequency rounded to three decimals.
Continue practicing

Related questions

TimingApply clock skew consistently→TimingInput-delay constraints from an external device→TimingChoose the direct fix for a hold violation→
asic.fyi · Learn silicon end to end.info@asic.fyi