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Hardware interview practice

Match out-of-order AXI read responses

HardUVMSystemVerilog

AXI read responses may reorder across IDs, but beats and bursts within one ID remain ordered. Design the scoreboard matching algorithm and its error rules.

Starting point

Question code

AR: id, address, len, accepted
R: id, data, resp, last, accepted
reset_n
maximum 16 IDs, 8 bursts per ID
Reviewed example

Work through one case

Input
Case 1: AR IDs 2 then 7
Case 2: Two ID-2 bursts
Case 3: After reset and before any new AR handshake, any accepted R beat
Expected output
Case 1: May return complete ID 7 before ID 2.
Case 2: Must return in their issue order even if ID 7 interleaves.
Case 3: Is UNEXPECTED; the checker does not invent a response epoch.

The shown result follows by applying this rule: The data structure expresses legal order per ID without imposing global order. The cases also demonstrate this requirement: On reset, flush all expected work. After release, match only responses to AR handshakes accepted after release and report any unmatched R beat as UNEXPECTED; AXI IDs alone cannot identify an old response after the same ID is reused.

What to cover

Requirements

  1. Keep a FIFO of expected bursts per ID, including expected data, response, and beat count.
  2. On each accepted R beat, compare against the head burst for RID and retire it only on the declared final beat.
  3. Reject an unknown ID, wrong data/response, early or missing RLAST, duplicate beat, and more than eight queued bursts per ID.
  4. On reset, flush all expected work. After release, match only responses to AR handshakes accepted after release and report any unmatched R beat as UNEXPECTED; AXI IDs alone cannot identify an old response after the same ID is reused.
Continue practicing
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