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Hardware interview practice

Identify sources of clock uncertainty

EasyStatic Timing AnalysisSystemVerilog

In a conventional STA setup check, what does clock uncertainty normally represent?

Choose one

Answer choices

  1. A. Only the receiving cell's setup time
  2. B. Margin for effects such as source or network jitter and residual skew not otherwise modeled
  3. C. Only data-path OCV derating
  4. D. The clock period itself
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