Hardware interview practice

Implement asynchronous FIFO full and empty logic

HardClock Domain CrossingSystemVerilog

Design the pointer, synchronization, memory, full, empty, and coordinated-reset behavior for a depth-16 dual-clock FIFO.

Starting point

Question code

// write: wclk, wrst_n, w_en, wdata, w_full
// read:  rclk, rrst_n, r_en, rdata, r_empty

Reviewed example

Input

Sixteen accepted writes and no reads

Expected output

w_full asserts after the sixteenth pointer advance

The next write Gray pointer reaches the state one buffer length ahead of synchronized read Gray.

What to cover

Use 5-bit binary/Gray pointers with a 4-bit memory address.
Register local Gray pointers and synchronize each Gray bus through two destination flops.
Register empty from next read Gray equaling synchronized write Gray; register full from next write Gray equaling synchronized read Gray with its top two bits inverted.
Treat reset as a coordinated flush and block both sides until both domains observe synchronized release.

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