Hardware interview practice
Glitch-free gated test clock
Enable changes must not shorten a gated-clock high pulse. Asserting reset is the sole exception and may force the gated clock low immediately. Write synthesizable SystemVerilog for the simple gate model.
Starting point
Question code
input logic clk, rst_n, enable;
output logic gclk;Reviewed example
Work through one case
Input
Stored enable is 0; external enable rises while clk is high, then clk reaches its falling edge.Expected output
gclk stays low during the current high phase; the next rising edge starts the first full gated-clock pulse.The gate samples enable only on the falling edge, isolating high-phase changes so they cannot shorten or create a partial pulse.
What to cover
Requirements
- Capture enable only on the falling edge of clk while rst_n is 1, then form gclk from clk AND the captured enable.
- Asynchronously clear the captured enable when rst_n is 0 so gclk is forced low; reset assertion is the only allowed cause of a shortened high pulse.
- A change in enable while clk is high must not change gclk until after the next falling edge.
- Use synthesizable logic without delays; state that a production ASIC would normally use a characterized integrated clock-gating cell.