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Hardware interview practice

Check a single-outstanding request/grant protocol

MediumProtocol VerificationSystemVerilog

Implement a clocked checker for one-cycle request pulses. Only one request may be pending, and its grant must arrive from 1 through 10 clocks after the request cycle.

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Starting point

Question code

input  logic clk, rst_n, req, grant;
output logic error;
Reviewed example

Work through one case

Input
req pulses at cycle 4; grant pulses at cycle 14
Expected output
pass, with error remaining 0

Cycle 14 is exactly ten rising edges after the request cycle, so it is the last legal grant cycle under the stated convention.

What to cover

Requirements

  1. Start counting only when a request is accepted while no request is pending.
  2. Flag a second request before the outstanding request completes.
  3. Accept a grant only 1 through 10 clocks after its request and treat an unsolicited grant as an error.
  4. Make error sticky until reset, and clear pending state, age, and error on reset.
Continue practicing

Related questions

Temporal ChecksAssert an integer square-root pipeline→Temporal ChecksCheck ordered grants for overlapping requests→Temporal ChecksOverlapped versus non-overlapped implication in SVA→
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