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asic.fyi

Hardware interview practice

Place a formal environment constraint

MediumAssertions and FormalSystemVerilog

A DUT accepts a request only when ready is high. The interface specification forbids the environment from changing the request payload while valid is high and ready is low. How should that rule normally be modeled when proving the DUT?

Choose one

Answer choices

  1. A. As an assertion on the DUT, because every signal at the DUT boundary is a DUT responsibility.
  2. B. As neither an assumption nor an assertion, because backpressure removes all protocol obligations.
  3. C. As an assumption on the environment, while DUT responses to legal transfers remain assertions.
  4. D. As a cover property, because cover automatically excludes illegal payload changes.
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