1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ919

Q919DVDesignASIC interview problem

Reassemble interleaved transactions by ID

TechniquesUVMMonitorInterleavingAssociative array

DifficultyHard

TopicUVM Components

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Extend a ready/valid monitor to reconstruct multi-beat transactions whose beats may interleave across transaction IDs. Publish only complete transactions.

Example input and output

Use this case to check your interpretation

Input

accepted beats: id1=A0 last=0; id2=B last=1; id1=A1 last=1

Output

publish transaction id2=[B], then id1=[A0,A1]

Explanation

Separate per-ID partial buffers allow id2 to complete between id1 beats without corrupting either assembly order.

Requirements (4)

Maintain independent partial assembly state for each ID.
Append a beat only on a valid/ready handshake and publish when that ID's last beat is accepted.
Flush every partial transaction on reset.
Assume at most one unfinished transaction per ID; state that a sequence tag is required otherwise.