1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ612

Q612DVDesignASIC interview problem

Monitor a ready/valid interface

TechniquesUVMMonitorAnalysis portReady/valid

DifficultyMedium

TopicUVM Components

LanguageSystemVerilog

Requirements4 checkpoints

Problem

Implement a passive UVM monitor for a single-beat ready/valid interface. Publish exactly one transaction for each observed handshake and remain safe across reset and unknown control values.

Example input and output

Use this case to check your interpretation

Input

successive samples: valid=1 ready=0; valid=1 ready=1 data=A; valid=X ready=1

Output

publish exactly one fresh transaction carrying A; report the unknown valid control

Explanation

The passive monitor observes only known-high handshakes and neither a stall nor an unknown control creates an analysis transaction.

Requirements (4)

Sample through a monitor clocking block and publish only when valid and ready are both known-high.
Flush or ignore observations while reset is not known-deasserted.
Report X or Z on handshake controls and on payload sampled during an accepted beat.
Construct the analysis port and publish a fresh transaction object for every accepted beat.