1,000+ ASIC Interview Questions: SystemVerilog, UVM & RTL

DescriptionQ894

Q894DVDesignIntelASIC interview problem

Select CDC structures for five signal classes

TechniquesDVDesignCDCClocking

DifficultyMedium

TopicDesign Verification

LanguageSystemVerilog

Requirements4 checkpoints

Problem

A subsystem has five crossings between unrelated source and destination clocks. Design the CDC plan and the structural checks for every crossing.

Starting declarationSystemVerilog

A enable_level: one bit, stable for at least 3 destination cycles
B irq_event: one source-cycle pulse; at most 3 events may be outstanding
C count[7:0]: monotonically increments by at most one per source edge
D stream: 32-bit ready/valid data with sustained traffic
E rst_n: asynchronous external reset into the destination domain

Example input and output

Use this case to check your interpretation

Input

Case 1: Issue two irq_event pulses before one destination edge
Case 2: Present a fourth event while three remain unconsumed
Case 3: Transfer words 10,11,12 through the asynchronous FIFO

Output

Case 1: the counted-event scheme produces two destination events
Case 2: the source contract is violated and the outstanding-count assertion fires
Case 3: each word is read exactly once and in order under any legal clock ratio

Explanation

The shown result follows by applying this rule: Match the crossing method to semantics: stable level, lossless event, constrained counter, arbitrary stream, or reset. The cases also demonstrate this requirement: For E, assert reset asynchronously and deassert it through a destination-domain reset synchronizer; run CDC/RDC checks for reconvergence, coherency, reset release, and illegal direct use of stage one.

Requirements (4)

Use a destination two-flop synchronizer for A, and do not edge-detect it until after synchronization if an event is needed.
For B, increment a 2-bit modulo-4 source event counter, transfer its Gray code to the destination, and emit at most one pulse per destination cycle while a local consumed counter differs. Return the consumed counter's Gray code to the source and assert that irq_event is low whenever the modulo distance is already three; coordinated reset clears both counters.
Register C as Gray code in the source, synchronize every Gray bit, constrain inter-bit skew, and decode only after synchronization; use an asynchronous FIFO for D.
For E, assert reset asynchronously and deassert it through a destination-domain reset synchronizer; run CDC/RDC checks for reconvergence, coherency, reset release, and illegal direct use of stage one.